Free Download Synopsys IC Compiler II W-2024.09-SP3 | 3.7 Gb
Synopsys IC Compiler II is a complete netlist-to-GDSII implementation system designed for semiconductor physical design workflows. It covers early design exploration and prototyping, design planning, block implementation, chip assembly, and signoff-driven design closure.
The software provides place-and-route capabilities for designs across different market segments and process technologies. Its workflow includes flat and hierarchical design planning, congestion-aware placement and optimization, clock tree synthesis, advanced-node routing, manufacturing compliance, and signoff closure.
IC Compiler II is designed to address performance, power, area (PPA), and time-to-market requirements in advanced semiconductor designs. Its optimization technologies include parallel processing, multi-objective global placement, routing-driven placement optimization, concurrent clock and data optimization, total power optimization, multi-pattern and FinFET-aware processing, and machine learning-driven optimization.