ESD Protection Device and Circuit Design for Advanced CMOS Technologies

The challenges associated with the design and implementation of Electrostatic Discharge (ESD) protection circuits are becoming increasingly complex as technology is scaled well into nano-metric regime. Traditional approaches of ESD design may not be adequate as the ESD damages occur at successively lower voltages in nano-metric dimensions. There are several challenges that must be met in order to design robust ESD circuits today. Due to technology scaling and proliferation of automated handling, ESD failures in ICs caused by Charged Device Model (CDM) are increasing. CDM discharges can cause latent damages which could degrade and eventually lead to definite failures in the ICs. The ESD protection design for current and future sub-65nm CMOS circuits is a challenge for high I/O count, multiple power domains and flip-chip products.
ESD Protection Device and Circuit Design for Advanced CMOS Technologies is intended for practicing engineers working in the areas of circuit design, VLSI reliability and testing domains. As the problems associated with ESD failures and yield losses become significant in the modern semiconductor industry, the demand for graduates with a basic knowledge of ESD is also increasing. Today, there is a significant demand to educate the circuits design and reliability teams on ESD issues. This book makes an attempt to address the ESD design and implementation in a systematic manner. A design procedure involving device simulators as well as circuit simulator is employed to optimize device and circuit parameters for optimal ESD as well as circuit performance. This methodology, described in ESD Protection Device and Circuit Design for Advanced CMOS Technologies has resulted in several successful ESD circuit design with excellent silicon results demonstrates its strengths.

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