VLSI Synthesis of DSP Kernels Algorithmic and Architectural Transformations

VLSI Synthesis of DSP Kernels presents the following:
Six different target implementation styles -
Programmable DSP-based implementation;
Programmable processors with no dedicated hardware multiplier;
Implementation using hardware multiplier(s) and adder(s);
Distributed Arithmetic (DA)-based implementation;
Residue Number System (RNS)-based implementation; and
Multiplier-less implementation (using adders and shifters) for fixed coefficient DSP kernels.
For each of the implementation styles, description and analysis of several algorithmic and architectural transformations aimed at one or more of reduced area, higher performance and low power;
Automated and semi-automated techniques for applying each of these transformations; and
Classification of the transformations based on the properties that they exploit and their encapsulation in a design framework. A methodology that uses the framework to systematically explore the application of these transformations depending on the characteristics of the algorithm and the target implementation style.
VLSI Synthesis of DSP Kernels is essential reading for designers of both hardware- and software-based DSP systems, developers of IP modules for DSP applications, EDA tools developers, researchers and managers interested in getting a comprehensive overview of current trends and future challenges in optimal implementations of DSP kernels. It will also be suitable for graduate students specialising in the area of VLSI Digital Signal Processing.
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VLSI Synthesis of DSP Kernels Algorithmic and Architectural Transformations Fast Download
VLSI Synthesis of DSP Kernels Algorithmic and Architectural Transformations Full Download