Udemy - Advanced VHDL for Verification

Advanced VHDL for verification, including TextIO, configurations, generics, records, BFM, multi-dimensional arrays, and access types.
Requirements
Experience in VHDL RTL design. Introduction to VHDL course completion recommended.
Description
The advanced VHDL course includes advanced RTL features as well as verification behavioral capabilities :
- VHDL Configurations
- VHDL Arrays
- Modeling memories in VHDL, creating inferred memories in RTL
- Modeling and inferring FIFOs in VHDL
- VHDL Signal Hierarchy
- VHDL Generics , Records, and Alias
- VHDL File I/O , and TextIO
- Creating pseudo-code for simulations
- Developing VHDL Bus Functional Models
Who this course is for:
VHDL RTL or Verification engineers who want to use the VHDL language to improve verification.

Homepage

https://www.udemy.com/course/advanced-vhdl-for-verification/