Udemy - Comprehensive Timing Constraints (SDC)

What you'll learn
Understand timing constraints and their importance
Each SDC command in detail
Constraints budgeting, promotion, verification, mode merging
Implementation vs STA timing constraints, CTS timing constraints
Requirements
Basics knowledge of digital design and STA
Description
Covers the following topics
· The role of timing constraints
· Timing constraints overview
· Clock Definitions
· Period
· Duty Cycle
· create_clock command
· Understanding various options of create_clock command
· Virtual clocks
· Generated clocks
· Where do define generated clocks
· create_generated_clock command
· create_generated_clock command options (-source, -edges, -edge_shift, -invert, -master
· Clock Groups
· Synchronous Clocks
· Asynchronous Clocks
· Logically Exclusive Clocks
· Physically Exclusive Clocks
· set_clock_groups command
· Multiple options of set_clock_group command
· Basics of Crosstalk
· set_clock_group command and crosstalk
· Clock characteristics
· Slew & Transition
· set_clock_transition command
· Skew and Jitter
· set_clock_uncertainty command
· Intra clock uncertainty
· Inter clock uncertainty
· Latency
· Source Latency and Network latency
· set_clock_latency command
· set_clock_sense command
· ideal network
· Port delays
· set_input_delay command
· set_output_delay command
· Additional boundary constraints
· set_drive
· set_driving_cell
· set_input_transition
· set_port_fanout_number
· set_fanout_load
· set_load
Path specification methods
· -from option
· -to option
· -through option
· Multiple throughs
· When -from/-to is clock
· -through f1/CK
· -rise_from/-fall_from
· -rise_from/-fall_from clock
· False paths
· set_false_path command
· False path gotchas
· Multicycle path
· set_multicycle_path
· setup mcp cycles
· hold mcp cycles
· -start option
· -end option
· Max and Min delays
· set_max_delay command
· set_min_delay command
· set_max_delay and set_min_delay gotchas
· Disable timing commands
· Case analysis command
· Miscellaneous commands
· set_operating_conditions
· set_timing_derate
· set_units
· set_hierarchy_separator
· set_wire_load_model
· set_max_area
· set_voltage
· set_voltage_area
· Level shifter commands
· Power Target commands
· Modes and Corners
· Signoff operating modes
· PVT Corners
· Multimode multicorner analysis
· Mode merging
· Number of modes and number of signoff runs
· Modes and ECO iterations
· Details of mode merging
· Individual mode vs merged mode pros and cons
· Constraints budgeting
· Why budgeting
· What is budgeting
· Constraints promotion
· Constraints promotion example
· Constraints verification
· Timing exceptions verification
· Implementation vs STA constraints
· Constraints for pre and post-CTS STA
Who this course is for
College ECE graduates, People looking to enter into semiconductor digital design, ASIC and FPGA freshers, Professionals planning to change field to digital design
Homepage

https://www.udemy.com/course/comprehensive-timing-constraints-sdc/

Udemy - Comprehensive Timing Constraints (SDC) Fast Download
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