Ip Verification Using System Verilog – Part I

What you'll learn
IP Verification concepts
Learning System Verilog Language for Verification
Developing System Verilog based testbench and testcases to verify a given IP
A Case study - how to verify an IP using SV
Requirements
Digital fundamentals
Verilog language
Basics of Verification
Description
System Verilog course content is designed for beginners to experts ; The modules can be learnt and practiced in couple of weeks: The detailed course syllabus is as follows: It is split into 2 partsSV - PART ISession 01 •Design verification and Verilog Refresh Lab 1 - Verilog Testbench developmentSession 02 •System Verilog Introduction, Data Types Lab 2 - Programs with Various data typesSession 03 •Control statements, Functions and Tasks Lab 3- SV Constructs practiceSession 04 •Arrays, Queues and OOPS, Classes Lab 4 - Arrays, Queues Constructs practiceSession 05 •Virtual Classes, Randomization, Constraints Lab 5- Classes, Randomization, Constraints. SV - PART IISession 06 •Inter process CommunicationLab 6- Use of mail box, Semaphores and QueuesSession 07 •Interfaces Lab 7-Use of interfaces, mod port, clocking blockSession 08 •BFM development Lab 8- Use of SV constructs for driver/BFMSession 09 •Code and Functional Coverage Lab 9-Simulate an example for coverageSession 10 •Test Plan and Project Lab 10 - Project workVarious example codes are explained in the course. Few of the programs are simulated in the industry standard simulators.A protocol example is also taken and testbench code is developed and test cases are written for the project.The assignment given helps to practice the code writing and further using for test bench and testcase development
Overview
Section 1: Verification in ASIC flow, System Verilog basics - Part I
Lecture 1 ASIC Flow, Introduction to SV
Lecture 2 SV Data Types
Lecture 3 SV Tasks, Functions and other advanced data types
Lecture 4 Queues, Arrays
Lecture 5 OOPS Concepts and Classes
Lecture 6 Lab Assignment
Internship for BE/MTech (ECE, EEE) students,Engineers who are beginners to System Verilog
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