Digital IC/FPGA Design P1: CMOS Gates & Arithmetic Datapath

Design SOC from basic bricks, solid foundation for building skyscrapers

What you'll learn

Basic theory of CMOS Gates
Use CMOS transistor to build any Logic Gates
Factors affect cell delay(PVT)
Behavior of Latch and DFF
Deep understanding for Setup/Hold time
Architecture of adder(ripple, carry-select, carry look ahead, tree adders)
Using architecture ideal of adders to optimize your design
Arithmetic operation on real number and any mathematic function
Technic support through Q&A system of Udemy

Requirements

Basic knowledge of digital fundamental
Basic C or C++ programing language

Description

I will try my best to explain what-> how-> why and encourage you to do it better.This is Part 1 of the whole course, introducing CMOS theory and arithmetic datapath. This's the foundation of design SOC.Contents in Part 1:Behavior and characteristics of CMOS gate: switch model, transition time, delay time, PVT corner.Using CMOS gate to build basic logic function gates: NAND, NOR, XOR, mUX.Build arithmetic datapth using basic logic gates: adder, subtractor, multiplier and divider. Learning the HW architecture ideas behind them to optimize your design.Once enrolled, you can get technic support through the Q&A system of Udemy.Let's cooperate and success.Note:Contents of the whole course (not just this part) :In the whole course, I will introduce fundamentals of digital IC and FPGA design, with 12+ coding exercises and 3 course projects.Theory part: MOS transistor -> logic cells -> arithmetic data path -> Verilog language -> common used HW function blocks and architecture -> STA -> on-chip-bus(APB/AHB-Lite/AXI4) -> low power design -> DFT -> SOC(MCU level).Function blocks and architecture: FSM, pipeline, arbiter, CDC, sync_fifo, async_fifo, ping-pong, pipeline with control, slide window, pipeline hazard and forward path, systolic.Project: SHA-256 algorithm with simple interface, SHA-256 with APB/AXI interface, 2D DMA controller with APB/AXI interface.After explaining of each HW architecture, I will give you a coding exercise, with reference code. Coding difficulty will begin from several lines to fifty lines, more than 100 lines, then around 200 lines. While the final big project will be 1000+ lines.I suppose these should be essential knowledge and skills you need master to enter this area.

Who this course is for

Senior undergraduate students of EE or higher
IC design/verification engineers with 0~2 years' experience
Homepage:

https://www.udemy.com/course/digital-icfpga-design-p1-cmos-gates-arithmetic-datapath/

Digital IC/FPGA Design P1: CMOS Gates & Arithmetic Datapath Fast Download
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